1. Field of the Invention
The present invention relates to reconfigurable computing systems.
2. State of the Art
As the cost of complex integrated circuits continues to fall, systems companies are increasingly embedding reduced instruction set computer (RISC) processors into non-computer systems. As a result, whereas the bulk of development work used to be in hardware design, now it is in software design. Today, whole applications, such as modems, digital video decompression, and digital telephony, can be done in software if a sufficiently high-performance processor is used. Software development offers greater flexibility and faster time-to-market, helping to offset the decrease in life cycle of today""s electronic products. Unfortunately, software is much slower than hardware, and as a result requires very expensive, high-end processors to meet the computational requirements of some of these applications. Field Programmable Gate Arrays (FPGAs) are also increasingly used because they offer greater flexibility and shorter development cycles than traditional Application Specific Integrated Circuits (ASICs), while providing most of the performance advantages of a dedicated hardware solution. For this reason, companies providing field programmable or embedded processor solutions have been growing very rapidly.
It is desired to have an improved method and apparatus for reconfigurable computing.
The present invention comprises placing address information along with configuration bits in blocks of data stored in an external memory. A reconfigurable chip uses the address data in the blocks to aide in the loading of the configuration bits in the correct locations of the reconfigurable logic.
Since address information is stored in the blocks, the blocks of configuration data stored in the external memory need not be stored in sequence. In prior art configurable systems, an entire configuration is typically loaded from the external memory in sequence, so that the correct loading of configuration data is maintained. The disadvantage of this prior art arrangement is that the entire sequence of configuration data stored in the external memory is relatively large, causing the loading time to be relatively large as well.
The arrangement of the present invention allows for less than all the configuration data to be stored in a downloaded group of the configuration blocks. Each block of data can be independently loaded. The address in the block of data is decoded to provide the reconfigurable chip address for storing the configuration bits. The position of a configuration bit block in the external memory is independent of the reconfigurable chip address stored in the block. This is an advantage in reconfigurable computing environments which use many partial loads of the reconfigurable chip with configuration data. The download time is reduced because not all of the configuration data needs to be downloaded from the external memory at one time.
In a preferred embodiment, each block comprises a line of data. The line of data is preferably sized to fit an internal bus of the reconfigurable chip. The configuration data can be for both the data paths and control path of the reconfigurable logic.
In a preferred embodiment, the loading of the configuration bits, is done using an address decoder to produce select lines. Each select line loads a number of memory elements with one of the configuration bits. There is preferably a configuration bit line is for each of the configuration bits in a block of configuration data. In one embodiment, there is a single such decoder and configuration bit line arrangement. Alternately, a decoder and configuration lines can be used for each of the slices used in the reconfigurable logic chip. The address in the block of configuration data can be an offset address from a base address. If multiple slices are used, a configuration allocation system can allocate the configurations to the correct slice.